Traditionally, checking for addressing errors such as address bus errors in electronic systems has largely been a lower priority than checking for data errors. However, in an effort to pursue maximum system reliability and availability, with respect to so-called “5-9's” carrier grade targets for instance, the need to detect all types of electronic system errors, including addressing errors, has become more important.
According to one electronic system error detection technique, a microprocessor writes data to a scratch pad register and then reads data from the same scratch pad register to verify an error-free data path between the microprocessor and the scratch pad register. However, this technique itself is susceptible to undetected addressing errors, in that an addressing error may affect both a write address and a subsequent read address. Thus, an incorrect register might be addressed during both write and read operations. In this case, the addressing errors would not be detected by the microprocessor.
Although other error protection techniques such as parity may be used to provide a level of protection against addressing errors, many system bus protocols which are employed within or between electronic systems or components thereof lack this kind of protection.